1. Field of the Invention
The present invention relates to a memory circuit which makes up a semiconductor dynamic RAM, more particularly, it relates to a memory circuit which is capable of executing accessing operations at extremely fast speed.
2. Description of Related Art
FIG. 1 schematically designates the block diagram of a conventional memory array. The reference numeral 1 shown in FIG. 1 designates an N-channel MOS transistor and the reference numeral 3 a sense amplifier. Gate of transistor 1 is connected to a work line WL, whereas source and drain of this transistor 1 are respectively connected to a capacitor 2 and a bit line B. The bit line B, the other bit line B, and a sense amplifier activating signal line SO, are respectively connected to the sense amplifier 3. The reference numerals 4 and 5 respectively designate N-channel MOS transistors each functioning as a transfer gate. Data signal "y" outputted from a conventional column decoder shown in FIG. 2 is inputted to gates of those transistors 4 and 5. The conventional column decoder shown in FIG. 2 incorporates a NAND circuit 23 and a NOT circuit 24 which are connected to each other in series. The NAND circuit 23 receives column address Ai. Source and drain of the N-channel MOS transistor 4 are respectively connected to the bit line B and a write/read signal line I/O. On the other hand, source and drain of the other N-channel MOS transistor 5 are respectively connected to the bit line B and the other write/read signal line I/O. A write buffer 21 and a read pre-amplifier 22 are respectively connected to the write/read signal lines I/O and I/O.
Referring now to the waveform chart shown in FIG. 3, functional operation of the conventional memory array incorporating the above structure is described below. The following description specifically refers to the bit-line pre-charging system applying 1/2 Vcc (Vcc: power voltage).
Initially, a pair of bit lines B and B are preliminarly charged with 1/2 Vcc. Next, one word line WL is selected by a low address, and then the selected word line WL goes High. As a result, capacitor 2 delivers a data signal to the bit line B, where the data signal contains "HIGH" information. This causes potential of the bit line B to become slightly higher than that of the other bit line B by about 100 mV. Next, the sense amplifier activating signal line SO goes High. This causes the sense amplifier 3 to amplify the potential of the High-level bit line B up to the Vcc potential and the Low-level bit line B down to the GND potential. This completes a refreshing operation f a dynamic RAM. Next, column address Ai turns the data "y" outputted from one column decoder High so that the output data "y" can be delivered to a pair of write/read signal lines I/O and I/O. The delivered data signal is then amplified by the read pre-amplifier 22 before being outputted from the dynamic RAM. On the other hand, data signal "y" outputted from the column decoder goes High, and then, data is written from the write buffer 21. These are the functional operations of the conventional operations of the conventional dynamic RAM for reading and writing data.
Since the conventional memory circuit incorporates the structure mentioned above, after completing data amplification by the sense amplifier, data signal is delivered to the write/read signal lines I/O and I/O. Because of this, any conventional dynamic RAM has those bit lines each containing substantial capacity. This in turn obliges the conventional system to take much time to execute amplification, thus eventually resulting in the delayed accessing operation. As a result, there is still substantial restriction to contract the cyclic time of the convention dynamic RAM.
To solve this problem, there is an idea to simultaneously activate the column decoder and the word line so that the accessing operation can be accelerated. Nevertheless, if the column decoder and the word line were simultaneously activated, since the bit line B is connected to the write/read signal line I/O containing substantial parasitic capacity, the bit-line capacity easily expands to merely lower the reading voltage. This in turn causes the memory system to easily malfunction itself. In consequence, any of those conventionally available memory systems cannot achieve accelerated accessing operation.